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350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ICS8402I Features
* * * * * * * * * * *
Two LVCMOS/LVTTL outputs Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK Output frequency range: 15.625MHz to 350MHz Crystal input frequency range: 12MHz to 40MHz VCO range: 250MHz to 700MHz Parallel or serial interface for programming counter and output dividers RMS period jitter: 30ps (maximum) Cycle-to-cycle jitter: 100ps (maximum) Full 3.3V or mixed 3.3V core/2.5V output supply -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
General Description
The ICS8402I is a general purpose, Crystal-to-LVCMOS/LVTTL High Frequency HiPerClockSTM Synthesizer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The ICS8402I has a selectable TEST_CLK or crystal inputs. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic. The low phase noise characteristics of the ICS8402I make it an ideal clock source for Gigabit Ethernet and SONET applications.
ICS
Block Diagram
OE0
Pin Assignment
VCO_SEL nP_LOAD XTAL_IN M4 M3 M2 M1 M0
OE1 VCO_SEL XTAL_SEL TEST_CLK XTAL_IN OSC XTAL_OUT 1 0 M5 M6 M7 M8 N0 N1 nc 1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16
VDD TEST
XTAL_OUT TEST_CLK XTAL_SEL VDDA S_LOAD S_DATA S_CLOCK MR
PLL
PHASE DETECTOR MR /M 0 1 /2 /4 /8 /16
GND
VCO
Q0
Q1 S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1 CONFIGURATION INTERFACE LOGIC
TEST
ICS8402I 32 Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32 Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View
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GND
OE1
OE0
Q1
VDDO
Q0
ICS8402I 350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Functional Description
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. The ICS8402I features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVCMOS output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8402I support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fXTAL x M The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 M 28. The frequency out is defined as follows: fout = fVCO = fXTAL x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: T1 0 0 1 1 T0 0 1 0 1 TEST Output LOW Shift Register Output Output of M Divider CMOS fOUT
SERIAL LOADING
S_CLOCK S_DATA
t
T1
S
T0
H
*Null N1
N0
M8
M7
M6 M5
M4
M3
M2
M1
M0
t
S_LOAD nP_LOAD
t
S
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
t
S
M, N
t
H
Time
*NOTE: The NULL timing slot must be observed.
Figure 1. Parallel & Serial Load Operations
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Table 1. Pin Descriptions
Number 1 2, 3, 4, 28, 29, 30, 31, 32 5, 6 7 8, 16 9 10 11, 12 13 14, 15 Name M5 M6, M7, M8, M0, M1, M2, M3, M4 N0, N1 nc GND TEST VDD OE1, OE0 VDDO Q1, Q0 Input Input Input Unused Power Output Power Input Power Output Pullup Type Pullup Description M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. Pulldown LVCMOS/LVTTL interface levels. Pulldown Determines output divider value as defined in Table 3C, Function Table. LVCMOS/LVTTL interface levels. No connect. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Output enable. When logic HIGH, the outputs are enabled (default). When logic LOW, the outputs are in Tri-State. See Table 3D, OE Function Table. LVCMOS / LVTTL interface levels. Output supply pin. Single-ended clock outputs. LVCMOS/LVTTL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the outputs to go low. When Logic LOW, the internal dividers and the Pulldown outputs are enabled. Assertion of MR does not affect loaded M, N, and T values. LVCMOS/LVTTL interface levels. Pulldown Pulldown Pulldown Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS/LVTTL interface levels. Analog supply pin. Pullup Selects between crystal oscillator or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS/LVTTL interface levels.
17
MR
Input
18 19 20 21 22 23 24, 25 26
S_CLOCK S_DATA S_LOAD VDDA XTAL_SEL TEST_CLK XTAL_OUT XTAL_IN nP_LOAD
Input Input Input Power Input Input Input
Pulldown Test clock input. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. Parallel load input. Determines when data present at M8:M0 is loaded into M Pulldown divider, and when data present at N1:N0 sets the N output divider value. LVCMOS/LVTTL interface levels. Pullup Determines whether synthesizer is in PLL or bypass mode. LVCMOS/LVTTL interface levels.
Input
27
VCO_SEL
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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Table 2. Pin Characteristics
Symbol CIN CPD RPULLUP Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V Test Conditions Minimum Typical 4 13 11 51 51 VDDO = 3.465V VDDO = 2.625V 5 7 7 12 Maximum Units pF pF pF k k
RPULLDOWN Input Pulldown Resistor ROUT Output Impedance

Function Tables
Table 3A. Parallel and Serial Mode Function Table
Inputs MR H L L L L L L L nP_LOAD X L H H H H H M X Data Data X X X X X N X Data Data X X X X X S_LOAD X X L L L H S_CLOCK X X X L L X S_DATA X X X Data Data Data X Data Conditions Reset. Forces outputs LOW. Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW H = HIGH X = Don't care = Rising edge transition = Falling edge transition
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Table 3B. Programmable VCO Frequency Function Table
VCO Frequency (MHz) 250 275 * * 650 675 700 256 M Divide 10 11 * * 26 27 28 M8 0 0 * * 0 0 0 128 M7 0 0 * * 0 0 0 64 M6 0 0 * * 0 0 0 32 M5 0 0 * * 0 0 0 16 M4 0 0 * * 1 1 1 8 M3 1 1 * * 1 1 1 4 M2 0 0 * * 0 0 1 2 M1 1 1 * * 1 1 0 1 M0 0 1 * * 0 1 0
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 25MHz.
Table 3C. Programmable Output DividerFunction Table
Inputs N1 0 0 1 1 N0 0 1 0 1 N Divider Value 2 4 8 16 Output Frequency (MHz) Minimum 125 62.5 31.25 15.625 Maximum 350 175 87.5 43.75
Table 3D. OE Function Table
Inputs OE0 0 0 1 1 OE1 0 1 0 1 Q0 Hi-Z Hi-Z Enabled Enabled Output Q1 Hi-Z Enabled Hi-Z Enabled
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VCC Inputs, VI Outputs, IO (LVCMOS) Package Thermal Impedance, JA 32 LQFP Package 32 VFQFN Package Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 47.9C/W (0 lfpm) 37C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V5%, VDDO = 3.3V5% or 2.5V5%, TA = -40C to 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage 2.375 Power Supply Current Analog Supply Current Output Supply Current 2.5 2.625 125 18 10 V mA mA mA Test Conditions Minimum 3.135 3.135 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 Units V V V
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Table 4B. LVCMOS/LVTTL DC Characteristics, TA = -40C to 85C
Symbol VIH Parameter Input High Voltage OE0, OE1, MR, M0:M8, N0, N1, S_CLOCK, S_DATA, S_LOAD, nP_LOAD, VCO_SEL, XTAL_SEL TEST_CLOCK TEST_CLOCK, MR, M0:M4, M6:M8, N0, N1, S_CLOCK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL, OE0, OE1 TEST_CLOCK, MR, M0:M4, M6:M8, N0, N1, S_CLOCK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL, OE0, OE1 VOH VOL Output High Voltage Output Low Voltage TEST; NOTE 1 Test Conditions Minimum 2 Typical Maximum VDD + 0.3 Units V
VIL
Input Low Voltage
-0.3
0.8
V
-0.3
1.3
V
IIH
Input High Current
VDD = VIN = 3.465V
150
A
VDD = VIN = 3.465V
5
A
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
A
VDD = 3.465V, VIN = 0V VDDO = 3.465V VDDO = 2.625V
-150 2.6 1.8 0.5
A V V V
TEST; NOTE 1
VDDO = 3.465 or 2.625V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Table 5. Input Frequency Characteristics, TA = -40C to 85C
Symbol Parameter TEST_CLK; NOTE 1 fIN Input Frequency XTAL_IN, XTAL_OUT; NOTE 1 S_CLOCK Test Conditions Minimum 12 12 Typical Maximum 40 40 50 Units MHz MHz MHz
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 M 58. Using the maximum input frequency of 40MHz, valid values of M are 7 M 17.
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Table 6. Crystal Characteristics
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance 12 Test Conditions Minimum Typical Fundamental 40 50 7 MHz Maximum Units
pF
AC Electrical Characteristics
Table 7A. AC Characteristics, VDD = VDDO = 3.3V5%, TA = -40C to 85C
Parameter Symbol fOUT tjit(cc) tjit(per) tsk(o) tR / tF tS Output Frequency Cycle-to-Cycle Jitter; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc tLOCK Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle PLL Lock Time 300MHz 20% to 80% 0.25 5 5 5 5 5 5 40 60 1 Test Conditions Minimum 15.625 40 8 Typical Maximum 350 100 30 80 1.1 Units MHz ps ps ps ns ns ns ns ns ns ns % ms
See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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Table 7B. AC Characteristics, VDD = 3.3V5%,VDDO = 3.3V5% or 2.5V5%, TA = -40C to 85C
Parameter Symbol fOUT tjit(cc) tjit(per) tsk(o) tR / tF tS Output Frequency Cycle-to-Cycle Jitter; NOTE 1, 3 Period Jitter, RMS; NOTE 1 Output Skew; NOTE 2, 3 Output Rise/Fall Time M, N to nP_LOAD Setup Time S_DATA to S_CLOCK S_CLOCK to S_LOAD M, N to nP_LOAD tH odc tLOCK Hold Time S_DATA to S_CLOCK S_CLOCK to S_LOAD Output Duty Cycle PLL Lock Time 300MHz 20% to 80% 0.25 5 5 5 5 5 5 40 60 1 Test Conditions Minimum 15.625 40 Typical Maximum 350 100 30 60 1.0 Units MHz ps ps ps ns ns ns ns ns ns ns % ms
See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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Parameter Measurement Information
1.65V5%
2.05V5% 1.25V5%
VDD, VDDA, VDDO
SCOPE
Qx
VCC, VCCA CCO V
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND VDDO 2
-1.65V5%
-1.25V5%
3.3/3.3V LVPECL Output Load AC Test Circuit
3.3V/2.5V LVPECL Output Load AC Test Circuit
VOH VREF VOL
Qx
Qy
tsk(o)
1 contains 68.26% of all measurements 2 contains 95.4% of all measurements 3 contains 99.73% of all measurements 4 contains 99.99366% of all measurements 6 contains (100-1.973x10-7)% of all measurements
Reference Point
(Trigger Edge)
Histogram
Mean Period
(First edge after trigger)
Output Skew
Period Jitter
V V
Q0, Q1
DDO
V
DDO
V
DDO
DDO
2 tcycle n
2
2 tcycle n+1
Q0, Q1
2
t PW
t
PERIOD
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
Cycle-to-Cycle Jitter
IDTTM / ICSTM LVCMOS/LVTTL FREQUENCY SYNTHESIZER
odc =
t PW t PERIOD
x 100%
Output Duty Cycle/Pulse Width/Period
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Parameter Measurement Information, continued
80% 20% tR
80% 20% tF
Clock Outputs
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8402I provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F VDDA .01F 10F 10
Figure 2. Power Supply Filtering
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Crystal Input Interface
The ICS8402I has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
XTAL_IN C1 22p X1 18pF Parallel Crystal XTAL_OUT C2 22p
Figure 3. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VCC
VCC
R1
Ro
Rs
50
0.1f
XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface
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Recommendations for Unused Input and Output Pins Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground.
Outputs:
LVCMOS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
TEST_CLK Input
For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the TEST_CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
VFQFN EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 5. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as "heat pipes". The number of vias (i.e. "heat pipes") are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount Assembly of Amkor's Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology.
PIN
SOLDER
EXPOSED HEAT SLUG
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
LAND PATTERN (GROUND PAD)
PIN PAD
Figure 5. P.C. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
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Reliability Information
Table 8A. JA vs. Air Flow Table for a 32 Lead LQFP
JA vs. Air Flow Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 67.8C/W 47.9C/W 200 55.9C/W 42.1C/W 500 50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 8B. JA vs. Air Flow Table for a 32 Lead VFQFN
JA vs. Air Flow Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 37C/W 1 32.4C/W 2.5 29.0C/W
Transistor Count
The transistor count for ICS8402I is: 3784
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Package Outline and Package Dimension
Package Outline - Y Suffix for 32 Lead LQFP
Table 9A. Package Dimensions for 32 Lead LQFP
JEDEC Variation: BBC - HD All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 1.60 A1 0.05 0.10 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D&E 9.00 Basic D1 & E1 7.00 Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 0.75 0 7 ccc 0.10 Reference Document: JEDEC Publication 95, MS-026
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Package Outline - K Suffix for 32 Lead VFQFN
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
are Even
OR
To p View
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
NOTE:The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not intended to convey the actual pin count or pin layout of this device. The pin count and pinout are shown on the front page. The package dimensions are in Table 8 below. Table 9B. Package Dimensions for 32 Lead VFQFN
JEDEC Variation: VHHD-2/-4 All Dimensions in Millimeters Symbol Minimum Nominal Maximum N 32 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.25 0.30 8 ND & NE D&E 5.00 Basic D2 & E2 3.0 3.3 e 0.50 Basic L 0.30 0.40 0.50 Reference Document: JEDEC Publication 95, MO-220
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ICS8402I 350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Ordering Information
Table 10. Ordering Information
Part/Order Number 8402AYI 8402AYIT 8402AYILF 8402AYILFT 8402AKI 8402AKIT 8402AKILF 8402AKILFT Marking ICS8402AYI ICS8402AYI ICS8402AYILF ICS8402AYILF ICS8402AKI ICS8402AKI ICS8402AKIL ICS8402AKI Package 32 Lead LQFP 32 Lead LQFP "Lead-Free" 32 Lead LQFP "Lead-Free" 32 Lead LQFP 32 Lead VFQFN 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN "Lead-Free" 32 Lead VFQFN Shipping Packaging Tray 1000 Tape & Reel Tray 1000 Tape & Reel Tray 2500 Tape & Reel Tray 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDTTM / ICSTM LVCMOS/LVTTL FREQUENCY SYNTHESIZER
17
ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I 350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
Revision History Sheet
Rev Table Page 1 6 12 13 13 14 16 17 Description of Change Pin Assignment - added 32 Lead VFQFN information. Absolute Maximum Ratings - added 32 Lead VFQFN package thermal impedance. Added LVCMOS to XTAL Interface section. Added Recommendations for Unused Input/Output Pins section. Added VFQFN EPAD Thermal Release Path section. Added 32 Lead VFQFN Reliability Information. Added 32 Lead VFQFN Package Dimensions Table and Package Outline Ordering Information Table - added 32 Lead VFQFN ordering information. Date
A
10/10/07
T9B T10
IDTTM / ICSTM LVCMOS/LVTTL FREQUENCY SYNTHESIZER
18
ICS8402AYI REV. A OCTOBER 16, 2007
ICS8402I 350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
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(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

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